1. Field of the Invention
The present invention is directed to the field of semiconductor processing, and, more particularly, to a method of forming titanium nitride layers on a semiconductor device.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. By way of background, an illustrative transistor 10 that may be included in such an integrated circuit device is shown in FIG. 1. The transistor 10 is generally comprised of a gate dielectric 14, a gate conductor 16, a plurality of source/drain regions 18 formed in a semiconducting substrate 12. The gate dielectric 14 may be formed from a variety of dielectric materials, such as silicon dioxide. The gate conductor 16 may also be formed from a variety of materials, such as polysilicon. The source and drain regions 18 may be formed by one or more ion implantation processes in which a dopant material is implanted into the substrate 12.
Next, a first dielectric layer 26 is formed above the transistor 10, and a plurality of vias or openings 24 are formed in the first dielectric layer 26. Thereafter, the vias 24 are filled with a conductive material, such as a metal, to form contacts or plugs 22. The contacts 22 are electrically coupled to the source and drain regions 18 of the transistor 10. Thereafter, a second dielectric layer 32 may be formed above the first dielectric layer 26. Multiple openings 30 may be formed in the second dielectric layer 32, and the openings 30 may thereafter be filled with a conductive material to form conductive lines 28. This interconnected network of contacts and lines allows electrical signals to propagate throughout the integrated circuit device. The techniques used for forming the various components depicted in FIG. 1 are known to those skilled in the art and will not be repeated here in detail.
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semiconducting substrate. One factor that affects the speed at which integrated circuit products operate is the speed at which electrical signals propagate through the device. Electrical signals travel within the device along the interconnected network of conductive lines and contacts. The greater the resistance of these lines and contacts, the slower the signals will propagate through the integrated circuit device, and the slower it will operate.
Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive inter-connections must be made in multiple layers to conserve plot space on the semiconducting substrate. This is typically accomplished through the formation of a plurality of conductive lines and conductive plugs located in layers of dielectric materials formed on the device. The conductive lines and plugs may be made of a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc.
Considerable effort goes into sizing, routing and selecting the appropriate materials for this vast collection of interconnections in an effort to minimize the resistance of the contacts and lines in the device such that device performance, i e., speed, is optimized or at least suitable for the design parameters of the particular product under construction. To form these conductive interconnections, i.e., lines and plugs, a layer of insulating material, such as silicon dioxide, is formed above the substrate or some other previously formed structure, i.e., another level of interconnections. Thereafter, openings are formed in the insulation layer by performing an etching process. Prior to forming a conductive line or plug in the opening, one or more barrier layers are formed in the opening. The purpose of the barrier layers is to, among other things, prevent migration of the metal used to form the conductive plug or line into the insulation layer.
In many situations, a combination of a layer of titanium nitride (TiN) and a layer of tungsten (W) is commonly employed to form this barrier layer. The purpose of the layer of titanium nitride is to, among other things, provide a better surface for the layer of tungsten to adhere to. Typically, the layer of titanium nitride is formed by a chemical vapor deposition (xe2x80x9cCVDxe2x80x9d) process, and it is subsequently subjected to a plasma treatment to remove certain residual materials from the layer of titanium nitride. These residual materials may include carbon, which is a remnant of certain precursor materials used to form the layer of titanium nitride.
The duration and temperature of the plasma treatment process performed on the titanium nitride layer is a function of the thickness of the titanium nitride layer. However, if the duration of the plasma treatment is too long or too short, the resistance of the layer of titanium nitride increases. This, in turn, results in a net increase in the overall resistance of the conductive contact or line. Moreover, as with most layers of material formed in a semiconductor fabrication facility, the thickness of a layer of titanium nitride may vary due to a variety of factors, e.g., variations in precursor materials, variations from one CVD tool to the next, etc. As a result, performing a standard plasma treatment on the titanium nitride layer based upon an assumed thickness of the layer of titanium nitride may be problematic when the layer of titanium nitride, as manufactured, is thinner or thicker than anticipated. That is, when the layer of titanium nitride is thicker or thinner than anticipated, performing a plasma treatment designed for an assumed thickness of the layer may result in increasing the resistance of the layer of titanium nitride. In turn, this increased resistance may tend to result in slower device performance.
The present invention is directed to a method of manufacturing semiconductor device that minimizes or reduces some or all of the aforementioned problems.
In general, the present invention is directed to a method of forming titanium nitride layers. In one illustrative embodiment, the method comprises forming a layer of titanium nitride by a chemical vapor deposition process, sensing a thickness of the layer of titanium nitride, and providing the sensed thickness of the layer of titanium nitride to a controller. The method further comprises determining at least one parameter of a plasma process to be performed on the layer of titanium nitride based upon the sensed thickness of the layer of titanium nitride and performing the plasma process comprised of the determined at least one parameter on the layer of titanium nitride.